Field
Embodiments described herein generally relate to methods for forming semiconductor devices, and more particularly to methods for forming fin field effector transistors (FinFETs).
Description of the Related Art
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 22 nm or smaller dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Recently, complementary metal oxide semiconductor (CMOS) FinFET devices have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices.
FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the FinFET devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of the FinFET devices include reducing the short channel effect and providing higher current flow.
To improve transistor performance, stressor materials may fill source/drain areas, and the stressor materials may grow in source/drain areas by epitaxy. The epitaxial film is faceted by {111} planes and has a diamond shape along the transistor channel direction. In other words, the epitaxial film may extend laterally and form facets. With the scaling down of transistors, fin pitch (distance between adjacent fins) is getting smaller. This may cause the reduction in the distance between an epitaxial film grown on a fin and an epitaxial film grown on an adjacent fin, which may cause adjacent epitaxial films to merge. The merged epitaxial films decreases the effect of epitaxial films on the strain in the transistor channel, and defects may form easily at the junction of the merged area.
Therefore, there is a need for an improved method for forming FinFETs.